1. Field of the Invention
The present invention relates generally to electrical interconnections and methods for interconnecting electronic components. More particularly, the present invention relates to electrochemical interconnections and processes for fabricating electrochemical interconnections by connecting semiconductor pads and their corresponding substrate pads with electroplated metal.
2. Description of the Related Art
An ongoing effort within the electronics industry has been to develop semiconductor configurations with increasingly smaller packaging requirements. At the same time, semiconductors are being designed with demanding functional requirements and high production costs. Thus, semiconductor packaging design configurations having relatively small packaging requirements and having high production yields are finding increased utility within the electronics industry.
One approach associated with this effort is a recent trend toward the use of high frequency circuits and a corresponding increase in the utility of flip chips. Flip chips can reliably accommodate shorter interconnections between their interconnect pads and pads on a substrate than other chip designs such as the Tape Automated Bonding (TAB) chips and wire bond chips. These shorter connections advantageously permit greater pad packing densities on substrates. Additionally, the flip chips can be more densely packed onto the available substrate space.
The short interconnection between semiconductor flip chip pads and the corresponding substrate chip pads are commonly formed using either a solder melt method or a cold weld indium bonding method. Typically flip chips have interconnection pads at the chip periphery which normally require 256 bonds. When using the solder melt method, solder on the flip chip pads must be precisely aligned with solder on the corresponding substrate pads so that the two parts intimately face each other. Furthermore, this position should be maintained during the thermal exposure cycle so that the solder on each pad not only melts but cross-wets the opposing solder to form a structurally sound bond with only the corresponding opposite mating surface. If the melted solder extrudes or splatters or there is excessive solder bulging, electrical shorting between adjacent pads can result.
Since pad alignment, solder mass, and the degree of the gap at the pad interface all have very close tolerances, effective solder melt methods require the use of expensive precision equipment for aligning the substrate pads and the flip chip pads and applying the solder. Another disadvantage is the thermal exposure experienced by the chip. In many cases this is not a problem, but some semiconductors are damaged or degraded by elevated temperatures. Moreover, semiconductors which are removed and then reconnected during a rework process may not tolerate a second thermal exposure. A further disadvantage is the typically low tensile strength of solder melt interconnect bonds. The ultimate tensile strengths associated with these bonds are about 7000 pounds per square inch (psi) or 48 megapascals. Bonds of this strength are prone to failure and this method is not recommended for structural purposes.
The cold weld indium bonding method for forming short interconnections between semiconductor chip pads and substrate pads requires indium or indium alloy bump pads on the semiconductor chip and on the substrate. Additionally, these bump pads must have a precise mass, geometry and height. In principle, the chip and the substrate are precision aligned and the indium bumps are brought into "squash" contact such that the indium on the chip pads bonds to the indium on the corresponding substrate pads by cold welding to each other. Bonding is completed at room temperature because the indium need not be melted.
Generally, the cold weld indium bonding method works well for its intended use. However, the bond can fail during thermal cycling testing if there is a thermal expansion mismatch between the semiconductor chip and the substrate. This phenomena combined with other problems such as control over the indium bump mass, the bump geometry, and alignment problems can result in process yields as low as 3%. Like the solder melt interconnect method, the indium cold weld method results in bonds having undesirably weak tensile strengths. The indium cold weld method typically has tensile strengths on the order of 400 psi or 2.75 megapascals and is not recommended for structural purposes.
It would be desirable to provide processes for interconnecting semiconductor chip pads with substrate pads which reliably produce interconnect bonds having a high tensile strength in high yields. It would also be desirable to provide processes for interconnecting semiconductor chip pads with substrate pads which can be performed at room temperature without expensive equipment and without subjecting semiconductor chips to possible thermal degradation.